TFTs are formed on an active matrix substrate of a liquid crystal display device. In a semiconductor device such as TFTs, in the process of forming lines by wet etching, etching defects tend to occur in the vicinity of step portions at lower layers of the lines. Because of this, in the process of producing the liquid crystal display device, for example, a line resistance is increased due to disconnection or partial disconnection of the lines, which sometimes decreases productivity and display quality. To deal with this, a line configuration has been proposed for suppressing the line width from being narrow in the step portion and the line from being disconnected (e.g., see Patent Document 1). Further, a configuration has been proposed that prevents disconnection of a drain line due to an etching liquid having been penetrated into a semiconductor layer pattern located at a gate/drain intersection and that prevents deterioration in coating properties of a protective insulating film (e.g., see Patent Document 2).